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ltc4310-1/ltc4310-2 1 431012fa typical a pplica t ion descrip t ion hot-swappable i 2 c isolators the ltc ? 4310 provides bidirectional i 2 c communications between two i 2 c buses whose grounds are isolated from one another. each ltc4310 encodes i 2 c bus logic states into signals that are transmitted across an isolation barrier to another ltc4310. the receiving ltc4310 decodes the transmission and drives its l 2 c bus to the appropriate logic state. the isolation barrier can be bridged by an inexpensive ethernet, or other transformer, to achieve communications across voltage differences reaching thousands of volts, or it can be bridged by capacitors for lower voltage isolation. the ltc4310-1 is intended for use in 100khz i 2 c systems. the ltc4310-2 is intended for 400khz i 2 c systems. rise time accelerators provide strong pull-up currents on scl and sda rising edges to meet rise time specifcations for heavily loaded systems. data and clock hot swap? circuitry prevent data corruption when a card is inserted into or removed from a live bus. when a bus is stuck low for 37ms, the ltc4310 turns off its pull-down devices and generates up to sixteen clocks and a stop bit in an attempt to free the bus. driving en low sets the ltc4310 in a very low current shutdown mode to conserve power. l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. hot swap is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. 1500v isolated i 2 c system fea t ures a pplica t ions n bidirectional i 2 c communication between two isolated buses n full isolation with inexpensive ethernet transformers or capacitors n low voltage level shifting n i 2 c maximum operating frequency: 100khz for ltc4310-1 400khz for ltc4310-2 n i 2 c specifcation compliant v ol , v il n 5kv human body model esd protection n rise time accelerators n sda, scl hot-swapping n very low shutdown current n stuck bus disconnect and recovery n thermal shutdown n 10-lead msop and 3mm 3mm dfn packages n isolated i 2 c, smbus and pmbus interfaces n isolated power supplies n positive-to-negative rail communications n power-over-ethernet ltc4310 operating through 20kv/s common mode transient rxp 10/100base-tx ethernet transformer epf8119s rxn txp sda scl en txn gnd ready 0.01f 0.01f isolated 5v 3.3v 3.3k 3.3k 3.3k 3.3k ltc4310-1 v cc sda2 scl2 sda1 scl1 0.01f 0.01f 431012 ta01a txp txn rxp rxn sda scl en ready gnd ltc4310-1 v cc 2s/div 20kv/s 0v 0v 500v/ div 2v/div 431012 ta01b sda scl
ltc4310-1/ltc4310-2 2 431012fa a bsolu t e maxi m u m r a t ings input supply voltage (v cc ) .......................... C0.3v to 6v input and bidirectional pin voltages scl, sda, en, rxp, rxn .......................... C0.3v to 6v output v oltages ready ..................................................... C0.3v to 6v txp, txn ...................... C0.3v to v cc + 0.3v (6v max) maximum sink current (sda, scl, ready) .......... 30ma (notes 1, 4) top view dd package 10-lead (3mm 3mm) plastic dfn 10 11 gnd 9 6 7 8 4 5 3 2 1 rxn rxp v cc txp txn en sda scl ready gnd t jmax = 125c, ja = 43c/w exposed pad (pin 11) pcb connection to ground is optional 1 2 3 4 5 en sda scl ready gnd 10 9 8 7 6 rxn rxp v cc txp txn top view ms package 10-lead plastic msop t jmax = 150c, ja = 120c/w p in c on f igura t ion or d er in f or m a t ion lead free finish tape and reel part marking* package description temperature range ltc4310cdd-1#pbf ltc4310cdd-1#trpbf lfch 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc4310idd-1#pbf ltc4310idd-1#trpbf lfch 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc4310cms-1#pbf ltc4310cms-1#trpbf ltfcg 10-lead plastic msop 0c to 70c ltc4310ims-1#pbf ltc4310ims-1#trpbf ltfcg 10-lead plastic msop C40c to 85c ltc4310cdd-2#pbf ltc4310cdd-2#trpbf lfck 10-lead (3mm 3mm) plastic dfn 0c to 70c ltc4310idd-2#pbf ltc4310idd-2#trpbf lfck 10-lead (3mm 3mm) plastic dfn C40c to 85c ltc4310cms-2#pbf ltc4310cms-2#trpbf ltfcj 10-lead plastic msop 0c to 70c ltc4310ims-2#pbf ltc4310ims-2#trpbf ltfcj 10-lead plastic msop C40c to 85c consult ltc marketing for parts specifed with wider operating temperature ranges. *the temperature grade is identifed by a label on the shipping container. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifcations, go to: http://www.linear.com/tapeandreel/ operating ambient temperature range l tc4310c ................................................ 0c to 70c l tc4310i .............................................. C40c to 85c storage temperature range dd ..................................................... C65c to 125c ms ..................................................... C65c to 150c lead t emperature (soldering, 10 sec) ms package ...................................................... 300c
ltc4310-1/ltc4310-2 3 431012fa e lec t rical c harac t eris t ics symbol parameter conditions min typ max units supplies v cc input supply range l 3 5.5 v i cc input supply current, ltc4310-1 input supply current, ltc4310-2 en = v cc = 5.5v, sda = scl = v sda,scl(ol) en = v cc = 5.5v, sda = scl = v sda,scl(ol) l l 6.5 7 8 8.5 ma ma i cc(sd) shutdown input supply current en = 0v, v cc = 5.5v l 0.1 10 a v cch(uvl) input supply undervoltage lockout rising threshold voltage l 2.1 2.4 2.7 v v cc(uvl, hyst) input supply undervoltage lockout hysteresis l 90 190 270 mv i 2 c interface v sda,scl(ol) sda, scl logic low output voltage i (sda,scl) = 4ma, 500a; v cc = 3v, 5.5v l 310 350 380 mv v sda,scl(il,r) sda, scl controlled rising edge rate turn-off threshold voltage v cc = 3v, 5.5v (note 5) l 0.3 ? v cc 0.35 ? v cc 0.4 ? v cc v v sda,scl(il,f) sda, scl logic low falling input threshold voltage v cc = 3v l 0.4 ? v cc 0.45 ? v cc 0.5 ? v cc v i sda,scl(oh) sda, scl input current sda = scl = 5.5v; v cc = 0v, 5.5v l 0 5 a i 2 c interface timing dv/dt rise bus line controlled rising edge rate, ltc4310-1 0.35v < v bus < 0.35 ? v cc , v cc = 3v 0.35v < v bus < 0.35 ? v cc , v cc = 5.5v l l 0.8 1.5 1.16 2.14 1.4 2.6 v/s v/s bus line controlled rising edge rate, ltc4310-2 0.35v < v bus < 0.35 ? v cc , v cc = 3v 0.35v < v bus < 0.35 ? v cc , v cc = 5.5v l l 2 3.9 3 5.4 3.9 6.9 v/s v/s t phl(sda,scl) sda, scl high-to-low propagation delay v cc = 5.5v (note 3) l 170 270 ns f scl(max) maximum scl clock frequency ltc4310-1 ltc4310-2 l l 100 400 khz khz c in scl, sda input capacitance scl, sda = v cc (note 2) 10 pf rise time accelerators v boost sda, scl rise time accelerator activation threshold voltage v cc = 3v (note 5) l 0.32 ? v cc 0.45 ? v cc 0.5 ? v cc v i boost sda, scl rise time accelerator current v cc = 3v l 2 6 ma ready open-drain output v ready(ol) ready output low voltage i ready = 4ma l 50 400 mv i ready(oh) ready off-current ready= v cc = 5.5v, en = 0v l 0.1 10 a connection control v en,rise en rising threshold voltage l 0.6 ? v cc 0.9 ? v cc v v en,fall en falling threshold voltage l 0.1 ? v cc 0.3 ? v cc v i en(oh) en input current en = v cc = 5.5v l 0.1 10 a t idle bus idle time l 75 115 155 s t uvlo,en_filt start-up filter time l 700 900 1200 s t stuck sda, scl bus stuck low disconnect l 27 37 47 ms the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v cc = 3.3v, unless otherwise noted.
ltc4310-1/ltc4310-2 4 431012fa symbol parameter conditions min typ max units t max(tx) maximum time between txp, txn transmit events l 0.85 1.15 1.45 ms t max(rx) maximum time between rxp, rxn receive events l 3.4 4.6 5.8 ms transmit outputs v tx(ol) txp, txn single-ended output low i sink = 100a, v cc = 3v l 1.5 5 mv v tx(oh) txp, txn single-ended output high 15k to gnd on txp, txn; v cc = 3v, 5.5v l 0.95 1.25 1.52 v t r(tx) txp, txn output rise time c txp , c txn = 20pf l 1 3 ns t f(tx) txp, txn output fall time c txp , c txn = 20pf l 1 3 ns t pwmin(tx) txp, txn minimum transmission pulse width v cc = 3v, 5.5v l 31.5 35 39 ns receive inputs v rx(th) rxp, rxn differential high level threshold rxp, rxn pins; v cc = 3v, 5.5v l 0.3 0.5 0.875 v t pwmin(rx) rxp, rxn minimum received pulse width v cc = 3v, 5.5v l 30 ns r rx(in) rxp, rxn differential input resistance l 13 16.5 20 k e lec t rical c harac t eris t ics the l denotes the specifcations which apply over the full operating temperature range, otherwise specifcations are at t a = 25c. v cc = 3.3v, unless otherwise noted. note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2. guaranteed by design, not tested in production. note 3. sda, scl high-to-low propagation delay is measured from the beginning of a new received message telling the ltc4310 to drive its sda, scl pins from high to low, to when the sda, scl lines have fallen below 0.5 ? v cc . it includes approximately 87ns required for an ltc4310 to receive a message on the rxp and rxn pins, plus the time the ltc4310 requires to process the message and pass the low to the data and clock buffers, plus the time required by the buffers to drive their bus pins below 0.5 ? v cc . note 4. all currents into pins are positive, all voltages are referenced to gnd unless otherwise specifed. note 5. internal control circuitry prevents the rise time accelerators from activating until the rising edge rate control circuitry is off.
ltc4310-1/ltc4310-2 5 431012fa typical p er f or m ance c harac t eris t ics sda, scl controlled rising edge rate vs temperature, ltc4310-1 sda, scl controlled rising edge rate vs temperature, ltc4310-2 sda, scl rise time accelerator pull-up current vs temperature sda, scl rise time accelerator pull-up current vs bus capacitance sda,scl falling propagation delay vs temperature i cc vs temperature, ltc4310-1 temperature (c) ?50 i cc (ma) 4.8 5.0 4.6 4.4 0 25 75 ?25 50 100 125 4.2 4.0 431012 g01 v cc = 3.3v v cc = 5v sda = 0v scl = v cc temperature (c) ?50 controlled rise rate (v/s) 1.6 1.8 1.4 1.2 0 25 75 ?25 50 100 125 2.0 431012 g02 v cc = 3.3v v cc = 5v temperature (c) ?50 controlled rise rate (v/s) 4.5 5.0 4.0 3.5 0 25 75 ?25 50 100 125 3.0 2.5 5.5 431012 g03 v cc = 3.3v v cc = 5v temperature (c) ?50 pull-up current (ma) 9 10 8 7 0 25 75 ?25 50 100 125 6 5 11 431012 g04 v cc = 3.3v v cc = 5v bus capacitance (pf) 0 pull-up current (ma) 8 10 6 4 200 300 500 100 400 600 700 800 2 0 12 431012 g05 v cc = 3.3v v cc = 5v t a = 25c temperature (c) ?50 propagation delay (ns) 180 200 160 140 0 25 75 ?25 50 100 125 120 0 220 431012 g06 v cc = 3.3v v cc = 5v
ltc4310-1/ltc4310-2 6 431012fa p in func t ions en (pin 1): device enable input. pulling en up to v cc sets the device in normal operation mode, allowing bus information to be sent and received across the barrier. grounding en disables communication across the bar - rier and debiases all internal circuitry, setting the device in a very low current shutdown mode. connect to v cc if unused. sda (pin 2): serial bus data input/output. this is the bidirectional data line for the two-wire bus. an external pull-up resistor or current source from sda to a supply voltage greater than or equal to the v cc voltage is required. see the applications information section for guidance on selecting the resistor or current source value. do not leave open. scl (pin 3): serial bus clock input/output. this is the bidirectional clock line for the two-wire bus. an external pull-up resistor or current source from scl to a supply voltage greater than or equal to the v cc voltage is required. see the applications information section for guidance on selecting the resistor or current source value. do not leave open. ready (pin 4): device receiving indicator output. ready is an open-drain digital output that pulls low when the ltc4310 is driving its sda and scl pins with the logic state information it is receiving on its rxp and rxn pins. connect this pin to v cc with a 10k resistor. this pin can be left open or tied to gnd if unused. gnd (pin 5): device ground. txn (pin 6): negative transmit output. tie txn to the negative side of the transformer primary winding or to the rxn pin of another ltc4310 through a ceramic capacitor. see the applications information section for guidance in selecting the capacitor value. do not leave open. txp (pin 7): positive transmit output. tie txp to the positive side of the transformer primary winding or to the rxp pin of another ltc4310 through a ceramic capacitor. see the applications information section for guidance in selecting the capacitor value. do not leave open. v cc (pin 8): device power supply input. connect a by- pass capacitor of at least 0.01f directly between v cc and gnd. rxp (pin 9): positive receive input. tie rxp to the posi- tive side of the transformer secondary winding or to the txp pin of another ltc4310 through a ceramic capacitor. see the applications information section for guidance in selecting the capacitor value. do not leave open. rxn (pin 10): negative receive input. tie rxn to the nega- tive side of the transformer secondary winding or to the txn pin of another ltc4310 through a ceramic capacitor. see the applications information section for guidance in selecting the capacitor value. do not leave open. exposed pad (pin 11) dfn package only: the exposed pad may be left open or connected to device ground.
ltc4310-1/ltc4310-2 7 431012fa f unc t ional diagra m 431012 fd + ? por circuitry 0.45 ? v cc 0.45 ? v cc rise rate limiter dv/dt rise v cc i boost rx falling v il rising v il uvlo sda 1.25v txp 1.25v txn stuck bus timers 8 2 7 + ? + ? 0.35 ? v cc + ? 0.35v 6 logic + ? 0.5v + ? 0.45 ? v cc 0.45 ? v cc rise rate limiter dv/dt rise v cc i boost rx falling v il rising v il scl 3 + ? en 1 + ? 0.35 ? v cc v cc + ? 0.35v logic t sd + ? 150a 150a rxp 9 rxn rxp rxn scl sda 10 ready 4 gnd 5 + ? 2.4v/2.21v + ? + ? + ? 0.5v + ? stop bit and bus idle detectors logic
ltc4310-1/ltc4310-2 8 431012fa o pera t ion the ltc4310 provides fully bidirectional communications between two i 2 c or smbus buses whose grounds are isolated from one another. clock stretching, clock syn - chronization, arbitration and data acknowledging all work seamlessly across the barrier, regardless of the locations of the master(s) and slave(s). referring to the application circuit shown in figure 1, an ltc4310 is located on each side of the isolation barrier. each ltc4310 contains logic detection circuitry that can differentiate externally driven sda and scl logic signals from its own output signals. each ltc4310 converts the logic state of the externally driven signals into a sequence of pulses that are then transmitted across the isolation bar - rier via an ethernet transformer (or coupling capacitors for low isolation voltage applications) to the other ltc4310. each ltc4310 also receives and decodes corresponding pulses from the other ltc4310 and drives its sda and scl pins accordingly. transmissions occur on the txp and txn pins in a sequence of 1.25v pulses. the ltc4310 receives messages on its rxp and rxn pins. signals having less than 500mv dif- ferential voltages are rejected to provide noise immunity against common-mode transients. when the ltc4310 receives a message to drive sda low, it regulates sda to 0.35v. if an external device pulls sda below 0.35v during this time, the ltc4310 detects this condition and immediately transmits a low to the other ltc4310. when an external pull-down device drives sda below 0.45 ? v cc from a logic high, txp and txn transmit a message across the isolation barrier instructing the other ltc4310 to drive its sda line low. when the external pull-down device turns off and sda is rising between 0v and 0.35 ? v cc , the ltc4310 limits the bus rise rate to dv/dt rise via the rise rate limiter circuitry. it also transmits a high to the other ltc4310. if the sda rise rate falls below the threshold, it is assumed that an- other pull-down on the bus has turned on and is pulling sda low, and a command to pull the far side low is sent across the isolation barrier. when sda rises above 0.35 ? v cc , the rise rate limiter circuitry is deactivated. when sda rises above 0.45 ? v cc , the rise time accelerator current i boost is activated, which provides a strong, slew-limited pull-up current to reduce system rise time. the ltc4310 contains power-on reset (por) circuitry that sets the data and clock pins in a high impedance state and deactivates the transmit and receive circuitry until the en voltage is high, the device is not in thermal shutdown and the v cc voltage is above the 2.4v uvlo threshold voltage. the ltc4310 enters thermal shutdown when the die temperature exceeds 150c. grounding en sets the ltc4310 in a near-zero current mode. after the ltc4310 exits por, stop bit and bus idle detector circuitry monitors the logic state of its own sda and scl bus and of the other i 2 c bus in the system via rxp and rxn. when a stop bit or bus idle occurs simultaneously on both i 2 c buses, the ltc4310 activates its sda and scl drivers, logic detection circuitry and rise time accelerators and drives ready low. the stuck bus timer and recovery circuitry disable the sda and scl driver, logic detection circuitry and rise time accelerators if the bus is low for 37ms. a stuck bus also causes ready to be released high. if the stuck bus releases high, the i 2 c driver and accelerator circuitry are reactivated when a stop bit or bus idle occurs simultane- ously on both i 2 c buses, as previously described. (ltc4310 refers to both ltc4310-1 and ltc4310-2)
ltc4310-1/ltc4310-2 9 431012fa figure 1. the ltc4310-1 in a transformer isolated application o pera t ion 10/100base-tx ethernet transformer epf8119s c1 0.01f c4 0.01f r3 10k r4 10k 3.3v r1 7.5k r2 7.5k r5 7.5k r6 7.5k is0lated 5v c bus = 40pf c bus = 80pf . . . slave slave#1 scl1 scl2 c3 0.01f c2 0.01f 431012 f01 txp 1 3 6 7 8 16 15 14 11 9 txn rxp rxn sda scl ready gnd gnd rxp rxn txp txn ready ltc4310-1 ltc4310-1 v cc en sda scl v cc en p slave#4
ltc4310-1/ltc4310-2 10 431012fa sda, scl bus pull-up resistor value selection when the sda (or scl) bus is rising between 0v and 0.35 ? v cc , the ltc4310 controls the bus rise rate to (0.35 ? v cc )/900ns for the ltc4310-1 and to (0.35 ? v cc )/ 300ns for the ltc4310-2. users must quantify their parasitic bus capacitance, c bus , and choose a bus pull- up resistor, r bus , based on their bus pull-up supply voltage and maximum bus switching frequency to en- sure that each bus rises faster than the controlled rise rate. for bus frequencies up to 100khz, choose the ltc4310-1 and refer to figure 2 for the maximum pull-up resistance to use. for bus frequencies between 100khz and 400khz, choose the ltc4310-2 and refer to figure 3 for the maximum pull-up resistance to use. be sure to include worst-case resistor tolerance when selecting resistor value. a pplica t ions i n f or m a t ion rise time accelerators the ltc4310s rise time accelerator circuitry on the sda and scl lines turns on during rising edges to reduce the bus rise time. when the bus has risen above 0.45 ? v cc , the ltc4310 turns on a strong, slew-limited pull-up current, i boost , to help even heavily loaded buses meet the rise time specifcations. see the typical performance characteristics section for the rise time accelerator pull-up current as a function of temperature and bus capacitance. when either the bus has risen above (v cc C 1v) or 300ns after the pull-up current has turned on (whichever comes frst), the ltc4310 deactivates its pull-up current to deter fghting with the subsequent falling edge. users must ensure that the bus pull-up supply voltage v bus v cc , so that the accelera- tors do not overdrive the sda, scl bus and source current into v bus . the rise time accelerators are deactivated during start-up, thermal shutdown, shutdown and after disconnec- tion due to a stuck bus or failure to receive a transmission within 4.6ms. figure 2. maximum sda,scl bus pull-up resistor value as a function of parasitic bus capacitance for the ltc4310-1 figure 3. maximum sda,scl bus pull-up resistor value as a function of parasitic bus capacitance for the ltc4310-2 c bus(max) (pf) 1 r bus(max) (k) 10 100 1000 431012 f02 v cc = 5v v cc = 3.3v 8 10 12 14 16 6 4 2 0 18 c bus(max) (pf) 1 r bus(max) (k) 10 100 1000 431012 f03 8 10 12 14 16 6 4 2 0 18 v cc = 5v v cc = 3.3v
ltc4310-1/ltc4310-2 11 431012fa a pplica t ions i n f or m a t ion figure 4. scl1 rising waveform of scl1 for application circuit shown in figure 1 figure 5. 100khz scl waveforms for application circuit shown in figure 1 bus rising edge waveform when all external pull-downs on scl1 (figure 1) turn off, the scl1 rising waveform will resemble that shown in figure 4. the ltc4310-1 senses that scl1 is rising and transmits a message to the other ltc4310-1 to release scl2 high. during the transmission, the frst ltc4310-1 also drives scl1 to 0.35v, so that when the transmission is complete, both buses will rise simultaneously from 0.35v at a rate of (0.35 ? v cc )/900ns. this functionality minimizes the effective skew between the two buses. when scl1 reaches 0.35 ? v cc , the ltc4310-1 deactivates its rise rate regulation circuitry. the bus then rises with a time constant of (r bus ? c bus ) until it reaches 0.45 ? v cc , at which point the i boost rise time accelerator pull-up current is activated. figure 5 shows scl1 and scl2 for an entire 100khz switching cycle. because the ltc4310-1 regulates the bus rise rate to (0.35 ? v cc )/900ns, the 5v bus signal rises more quickly than the 3.3v bus signal. both buses reach (0.35 ? v cc ) in approximately 900ns, so the effective skew between the buses is nearly zero. the ltc4310-2 functions the same as the ltc4310-1, except the controlled rise rate is limited to (0.35 ? v cc )/300ns. 1v/div 200ns/div bus rc 431012 f04 scl1 set to 0.35v during tx rise time accelerator active 0.35 ? v cc 900 ns dv/dt = 1v/div 2s/div scl1 scl2 431012 f05 start-up, data and clock hot swap circuitry the ltc4310 contains power-on reset (por) circuitry that sets the data and clock pins in a high impedance state and deactivates the transmit circuitry until the en voltage is high, the device is not in thermal shutdown and the v cc voltage is above 2.4v. after the ltc4310 exits the por state, it activates its transmit circuitry and communicates its sda, scl logic states across the barrier to the other ltc4310 via its txp and txn pins. the receive circuitry remains deactivated for an additional 900s after the ltc4310 exits por. the 900s flter time is required for the ltc4310 to charge its rxp and rxn pins to their dc bias voltage, assuming a 0.01f common-mode noise fltering capacitor at the center-tap of the secondary side of the external transformer. when the flter time has elapsed, the ltc4310 activates its receive circuitry and decodes the messages it receives on its rxp and rxn pins, registering the logic state of the remote i 2 c bus. when both the local and remote two-wire buses are quiet (i.e., no data transactions are occurring on either bus), the ltc4310 then drives its ready pin low to indicate that it has linked the logic state of the local i 2 c bus with the logic state of the remote i 2 c bus. this means that the ltc4310 will now drive its sda and scl pins to the logic state of the remote i 2 c bus, as specifed by the messages it receives on rxp and rxn. the ltc4310 considers a two-wire bus
ltc4310-1/ltc4310-2 12 431012fa a pplica t ions i n f or m a t ion quiet if it has been idle high for at least 115s, or if a stop bit has occurred and both data and clock have remained high since the stop bit. this functionality makes the ltc4310 ideal for hot-swapping cards into and out of a live i 2 c system. the threshold voltages for the stop bit and bus idle comparators are 0.5 ? v cc . stuck bus disconnect and recovery an internal timer runs whenever sda, scl or both are low. the timer is only reset when both sda and scl are high. if the timer does not reset within 37ms, the ltc4310 assumes the bus is stuck low. accordingly, it ceases driving its sda and scl pins and transmits a special message across the barrier to inform the other ltc4310. upon receiving this message, the other ltc4310 also ceases driving its sda and scl pins. at least 40s after determining the bus is stuck low, the ltc4310 generates up to sixteen clock cycles on scl in an attempt to make the slave release the sda line. the ltc4310 stops issuing clocks when the sda line releases high, or after sixteen cycles, whichever comes frst. once the clock pulses have completed, the ltc4310 issues a stop bit on sda and scl to reset all devices on the bus. the ltc4310 reactivates its amplifers and rise time ac- celerators when the bus releases high and a stop bit or bus idle occurs on both the local and isolated buses, as previously described in the start-up, data and clock hot swap circuitry section. the stuck bus disconnect and re - covery circuitry is disabled when the ltc4310 is in uvlo, thermal shutdown and low current shutdown. transmit and receive circuitry transmissions occur on the txp and txn pins whenever the externally driven sda or scl logic state changes C in other words, transmissions are event driven. in addition, if sda and scl do not change state for 1.15ms, the ltc4310 retransmits the logic state. the txp and txn pins are driven in a pseudo differential fashion. both pins are driven to ground when inactive and are driven to 1.25v (typical) in matched sets of alternating 35ns pulses to send information across the barrier to the other ltc4310. the ltc4310 receives and decodes the pulses sent by the other ltc4310 on its rxp and rxn pins. assuming the start-up sequence previously described has been com - pleted, the ltc4310 drives its sda and scl lines to the logic state dictated by the decoded rxp and rxn signals. the ltc4310 rejects rxp and rxn signals having less than 500mv magnitude to provide noise immunity against common-mode transients.the parasitic capacitances of the ltc4310s rxp and rxn pins and their associated board traces form a capacitive divider with the transmit/receive coupling capacitors, as shown in figure 6. to guarantee robust communications, minimize the parasitic capacitance cpar by minimizing the trace length from the coupling capacitors to the rxp and rxn pins and choose coupling capacitor values, crxp and crxn, that are at least ten times larger than cpar. figure 6. parasitic trace and pin capacitances form a capacitive divider with c rxp and c rxn . ensure c rxp , c rxn 10 ? c par 431012 f06 crxp 47pf crxn 47pf gnd rxp rxn ltc4310 cpar1 4.7pf cpar2 4.7pf if the ltc4310 has not received a message in 4.6ms, it assumes there is a communication problem and ceases driving its sda and scl pins. it also transmits a special message to the other ltc4310 to inform it that it is no longer driving its sda and scl bus. upon receiving this message, the other ltc4310 also ceases driving its sda and scl pins. once the communication problem is resolved, both ltc4310s reactivate their amplifers and rise time accelerators after a stop bit or bus idle has occurred on both buses, as previously described in the start-up, data and clock hot swap circuitry section. thermal shutdown if the die temperature of the ltc4310 exceeds 150c, the ltc4310 enters a thermal shutdown mode. it sets txp and txn to a high impedance state, ceases driving sda and scl, and ignores the signals on rxp and rxn. when the temperature drops back below 130c, the ltc4310 goes through the por sequence previously described.
ltc4310-1/ltc4310-2 13 431012fa once a stop bit or bus idle occurs on both the local and is olated buses, the ltc4310 reactivates its buffers and rise time accelerators. ready digital output the ready pin provides a digital output fag that pulls low to indicate that the ltc4310 is driving its sda and scl pins with the logic state information it is receiving on its rxp and rxn pins from the other ltc4310. ready is driven by an n-channel mosfet open-drain pull-down that is capable of sinking 4ma while holding 0.4v maximum. the pull-down turns off whenever the ltc4310 is not driving its sda and scl pinsduring start-up, thermal shutdown, low current shutdown and after disconnection due to a stuck bus or failure to receive a transmission within 4.6ms. connect a resistor to the bus pull-up supply to provide the pull-up. design example: high voltage isolation using an inexpensive ethernet transformer figure 1 shows the ltc4310-1 providing i 2 c communi- cations between two buses whose ground voltages can differ up to 1500v. an epf8119s ethernet transformer is u sed to bridge the isolation barrier. the left i 2 c bus con - nects to the ltc4310-1 and two other devices, resulting in a bus parasitic capacitance of 40pf in this example set-up. referring to the v cc = 3.3v curve in figure 2, 7.5k pull-up resistors are chosen for r1 and r2. the right i 2 c bus connects to another ltc4310-1 and four slave devices, resulting in a bus parasitic capacitance of 80pf. referring to the v cc = 5v curve in figure 2, 7.5k pull-up resistors are also chosen for r5 and r6. standard 5% resistors are used. sudden changes in the ground differential across the isolation barrier can be effectively resisted by tying the center tap of the receive side of the transformer to the local ground through a 0.01f capacitor, as shown by capacitors c2 and c3. figure 7 shows the same application as figure 1, but with each ltc4310-1 replaced by an ltc4310-2, so that the bus can switch at frequencies up to 400khz. to meet the requirements shown in the curves of figure 3, r1 and r2 are changed from 7.5k to 4.3k, and r5 and r6 are changed from 7.5k to 3.3k. a pplica t ions i n f or m a t ion figure 7. the ltc4310-2 in a 400khz application epf8119s c1 0.01f c4 0.01f 3.3v r1 4.3k r2 4.3k r5 3.3k r6 3.3k . . . slave slave#1 scl1 scl2 c3 0.01f c2 0.01f 431012 f07 txp txn rxp rxn sda scl ready gnd gnd rxp rxn txp txn ready ltc4310-2 ltc4310-2 v cc en sda scl v cc en p slave#4 r3 10k r4 10k is0lated 5v 10/100base-tx ethernet transformer c bus = 40pf c bus = 80pf 1 3 6 7 8 16 15 14 11 9
ltc4310-1/ltc4310-2 14 431012fa a pplica t ions i n f or m a t ion t ypical a pplica tions figure 8 shows the ltc4310-1 providing i 2 c communica- tions between an i 2 c bus referenced to system ground and an i 2 c bus using C5v for its ground reference. ceramic coupling capacitors, c1-c5, are used to bridge the isolation barrier. this circuit is recommended for ground isolation voltages less than 100v and is limited by the voltage rating of c1-c5. higher voltage ceramic capacitors may be used to achieve higher isolation voltages. because the ltc4310 uses a pseudo-differential transmit scheme, capacitor c5 must be connected between ground and C5v to provide a return path for the transmitted current. figure 9 shows the ltc4310-1 in an application circuit using its zero current shutdown mode. a microprocessor only activates the left ltc4310-1 when it needs to com - municate with the isolated i 2 c bus. because the ltc4310-1 contains a stop bit and bus idle detection circuitry, there is no danger of connecting in the middle of a message when the microprocessor asynchronously reenables the ltc4310-1. figure 8. low voltage i 2 c isolation between a ground referenced bus and a C5v referenced bus 3.3v c bus = 30pf c bus = 100pf r1 5.1k r2 5.1k r3 10k 431012 f08 c7 0.01f c1 ?5v ?5v r5 10k r6 10k gnd rxp rxn txp txn ltc4310-1 v cc ready en sda scl r4 10k c3 c2 c4 c6 0.01f gnd txp txn rxp rxn ltc4310-1 v cc ready en sda scl c5 c1 to c5 = 47pf, 100v figure 9. the ltc4310-1 in a zero current shutdown application 5v r1 3.3k r2 3.3k r3 10k 431012 f09 c7 0.01f ?5v ?5v r5 5.1k r6 5.1k gnd rxp rxn txp txn ltc4310-1 v cc ready en sda scl r4 10k c6 0.01f gnd txp txn rxp rxn ltc4310-1 v cc ready en sda scl . . . slave#1 p slave#n on off c1 c3 c2 c4 c5 c1 to c5 = 47pf, 100v c bus = 150pf c bus = 200pf
ltc4310-1/ltc4310-2 15 431012fa a pplica t ions i n f or m a t ion figure 10. the ltc4310-1 in an i 2 c hot-swapping application 5v backplane connector backplane card connector r1 2k r2 2k r3 10k i/o peripheral card 431012 f10 c7 0.01f r5 6.8k r6 10k r7 100k gnd rxp rxn txp txn ltc4310-1 v cc ready en sda scl ready en sda scl ready2 en2 sda2 3.3v scl2 r4 6.8k c6 0.01f gnd txp txn rxp rxn ltc4310-1 v cc ready en sda scl c1 c3 c2 c4 c5 c1 to c5 = 47pf, 100v c bus = 50pf c bus = 400pf figure 10 shows the ltc4310-1 in a two-wire bus hot swap application. using a staggered connector, make en the shortest length pin to ensure that the transients associated with hot swapping have settled before the ltc4310-1 can be enabled. after connection is complete, a master on the backplane may drive en high to bring the ltc4310-1 out of shutdown mode and into normal operation. due to its stop bit and bus idle detection circuitry, the ltc4310-1s driver circuitry is not activated until transactions on both buses are complete. ltc4310 compatibility with other ltc bus buffers the ltc4310 cannot be used on the same i 2 c bus with the ltc4300a-1, ltc4303 or ltc4307. during rising edges, the rise time accelerators of these buffers turn on before the ltc4310 disables its rise rate regulation circuitry, resulting in nonmonotonic bus edges. the ltc4310-1 is compatible with the ltc4301 and ltc4301l. it is also compatible with the ltc4302, ltc4304, ltc4305 and ltc4306, provided that the rise time accelera - tors of these buffers are permanently disabled. all of the previously mentioned buffers are incompatible with the ltc4310-2 because the compensation networks of these buffers cause the bus to rise more slowly than (0.35 ? v cc )/300ns, therefore the ltc4310-2 would not be able to control the bus rise rate. ltc4310-1 compatibility with ltc4310-2 in a typical application such as shown in figure 1, an ltc4310-1 can be used on one bus and an ltc4310-2 can be used on the other, provided that the bus pull-up resis - tors connected to the ltc4310-1 meet the requirements of figure 2, and the bus pull-up resistors connected to the l tc4310-2 meet the requirements of figure 3. however, the bus switching frequency is limited by the rise rate regulation circuitry of the ltc4310-1. in addition, signifcant skew is introduced on the rising edges due to the large difference in the controlled rise rates of the two buses. for this reason, it is recommended to use two ltc4310-1s in smbus and standard mode i 2 c applications and to use two ltc4310-2s in fast mode i 2 c applications. the ltc4310-1 cannot be used on the same physical i 2 c bus with the ltc4310-2, because the ltc4310-1s rise rate regulation circuitry controls the bus rise rate to (0.35 ? v cc )/900ns, therefore the ltc4310-2 would not be able to control the bus rise rate.
ltc4310-1/ltc4310-2 16 431012fa using the ltc4310-1 at frequencies above 100khz users who implement custom two-wire buses may use the ltc4310-1 at bus frequencies above 100khz provided that all other devices on the bus can tolerate the approximately 1s bus rise times resulting from the ltc4310-1s bus rise rate regulation circuitry. transformer selection guide as shown in figure 1, a transformer passes transmit and receive signals between the two ltc4310s. the transmit signals have 1.25v magnitude and 35ns pulse width. the receive circuitry has an equivalent input impedance of 16.5k and can receive differential signals ranging from 0.875v to 1.55v. to meet these requirements, choose a transformer having a magnetizing inductance ranging from 50h to 350h, a 1:1 turns ratio and a maximum insertion loss of C1.5db. for optimal common mode noise rejection, choose a center-tapped transformer and connect the center tap on the receiving side to local ground using a 0.01f capacitor. ringing at the ltc4310s rxp and rxn pins can effectively be damped by inserting 50 series resistors between each ltc4310s txp and txn pins and the corresponding transformer primary windings. table 1 shows a recommended list of transformers for use with the ltc4310. 10/100basetx ethernet transformers are inexpensive and work very well in this application for isolation voltages up to 1500v. for applications requiring 4000v isolation, the wrth electronics midcom 749014012 transformer is recommended. rf radiated emissions the ltc4310 evaluation board passes cispr22 class b re quirements for radiated emissions. the results of cispr22 testing are shown in the evaluation board manual. to reduce radiated emission levels further, enclose the ltc4310 application circuit in a shielded enclosure. common mode transient immunity the ltc4310 has high immunity to common mode tran - sients. this is tested by applying a square voltage pulse having very fast edges between the isolated grounds. the ltc4310 passes 20kv/us edges without corruption of the i 2 c bus logic states. table 1. ltc4310 recommended transformers manufacturer part number isolation voltage form factor (mm) turns ratio center tap operating temperature x y z pca electronics epf8119s 1500v rms 10.41 12.45 5.84 1:1 yes 0c to 70c epf8119se 1500v rms 10.2 12.7 5.96 1:1 yes C40c to 85c pulse e5017 1500v rms 9.4 12.7 5.08 1:1 yes 0c to 70c wrth electronics midcom 000-7090-37r-lf1 1500v rms 9.4 12.95 5.33 1:1 yes C40c to 85c 749014012 4000v rms 17 24.55 10.85 1:1 yes 0c to 70c a pplica t ions i n f or m a t ion
ltc4310-1/ltc4310-2 17 431012fa dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) p ackage descrip t ion 3.00 0.10 (4 sides) note: 1. drawing to be made a jedec package outline m0-229 variation of (weed-2). check the ltc website data sheet for current status of variation assignment 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.15mm on any side 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package 0.40 0.10 bottom view?exposed pad 1.65 0.10 (2 sides) 0.75 0.05 r = 0.125 typ 2.38 0.10 (2 sides) 1 5 10 6 pin 1 top mark (see note 6) 0.200 ref 0.00 ? 0.05 (dd) dfn rev c 0310 0.25 0.05 2.38 0.05 (2 sides) recommended solder pad pitch and dimensions 1.65 0.05 (2 sides) 2.15 0.05 0.50 bsc 0.70 0.05 3.55 0.05 package outline 0.25 0.05 0.50 bsc dd package 10-lead plastic dfn (3mm 3mm) (reference ltc dwg # 05-08-1699 rev c) pin 1 notch r = 0.20 or 0.35 45 chamfer
ltc4310-1/ltc4310-2 18 431012fa p ackage descrip t ion ms package 10-lead plastic msop (reference ltc dwg # 05-08-1661 rev e) msop (ms) 0307 rev e 0.53 0.152 (.021 .006) seating plane 0.18 (.007) 1.10 (.043) max 0.17 ?0.27 (.007 ? .011) typ 0.86 (.034) ref 0.50 (.0197) bsc 1 2 3 4 5 4.90 0.152 (.193 .006) 0.497 0.076 (.0196 .003) ref 8910 7 6 3.00 0.102 (.118 .004) (note 3) 3.00 0.102 (.118 .004) (note 4) note: 1. dimensions in millimeter/(inch) 2. drawing not to scale 3. dimension does not include mold flash, protrusions or gate burrs. mold flash, protrusions or gate burrs shall not exceed 0.152mm (.006") per side 4. dimension does not include interlead flash or protrusions. interlead flash or protrusions shall not exceed 0.152mm (.006") per side 5. lead coplanarity (bottom of leads after forming) shall be 0.102mm (.004") max 0.254 (.010) 0 ? 6 typ detail ?a? detail ?a? gauge plane 5.23 (.206) min 3.20 ? 3.45 (.126 ? .136) 0.889 0.127 (.035 .005) recommended solder pad layout 0.305 0.038 (.0120 .0015) typ 0.50 (.0197) bsc 0.1016 0.0508 (.004 .002)
ltc4310-1/ltc4310-2 19 431012fa information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa - tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 4/11 revised conditions for i sdd,scl(oh) in the electrical characteristics section. 3
ltc4310-1/ltc4310-2 20 431012fa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com linear technology corporation 2010 lt 0411 rev a ? printed in usa r ela t e d p ar t s typical a pplica t ion part number description comments ltc4300a-1/ltc4300a-2/ ltc4300a-3 hot-swappable 2-wire bus buffers ltc4300aC1: bus buffer with ready and enable, ltc4300aC2: dual supply bus buffer with v cc2 and acc, ltc4300aC3: dual supply bus buffer with v cc2 and enable ltc4301 supply independent hot-swappable 2-wire bus buffer supply independent ltc4302-1/ltc4302-2 addressable 2-wire bus buffer address expansion, gpio, software controlled ltc4303/ltc4304 hot-swappable 2-wire bus buffer with stuck bus recovery provides automatic clocking to free stuck i 2 c busses ltc4305/ltc4306 2- or 4-channel, 2-wire bus multiplexers with capacitance buffering two or four selectable downstream busses, stuck bus disconnect, rise time accelerators, fault reporting, 10kv hbm esd tolerance ltc4307 low offset hot-swappable 2-wire bus buffer with stuck bus recovery 60mv buffer offset, 30ms stuck bus disconnect and recovery, rise time accelerators, 5kv hbm esd tolerance ltc4307-1 high de f nition multimedia inter face (hdmi) level shifting 2-wire bus buffer, 60mv buffer offset, 3.3v to 5v level shifting, 5kv hbm esd tolerance ltc4308 low voltage level shifting hot-swappable 2-wire bus buffer with stuck bus recovery C200mv offset in-out/+300mv offset out-in, 0.9v to 5.5v level shifting, 30ms stuck bus disconnect and recovery, output side rise time accelerators, 6kv hbm esd tolerance ltc4309 level shifting low offset hot-swappable 2-wire bus buffer with stuck bus recovery 60mv buffer offset, 30ms stuck bus disconnect and recovery, rise time accelerators, 1.8v to 5v level shifting, 5kv hbm esd tolerance ltc4311 i 2 c/smbus rise time accelerator strong slew limited current source, wide 1.6v to 5.5v supply range, auto detect low power standby, low <5a supply shutdown current, 8kv hbm esd tolerance breaking ground loops using capacitors 3.3v 5v r1 5.1k r2 5.1k r3 10k 431012 ta02 c7 0.01f r5 10k r6 10k gnd rxp rxn txp txn ltc4310-1 v cc ready en sda scl r4 10k c6 0.01f gnd txp txn rxp rxn ltc4310-1 v cc ready en sda scl c1 c3 c2 c4 c5 c1 to c5 = 47pf, 100v c bus = 20pf c bus = 100pf

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